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Full Scan Fault Coverage With Partial Scan.

, , and . DATE, page 468-472. IEEE Computer Society / ACM, (1999)

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Using dynamic shift to reduce test data volume in high-compression designs., , and . ETS, page 1-6. IEEE, (2014)Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits., , and . VLSID, page 399-404. IEEE Computer Society, (2015)Detecting and diagnosing open defects., , , , , and . ITC, page 811. IEEE Computer Society, (2010)On Improving Transition Test Set Quality to Detect CMOS Transistor Stuck-Open Faults., , and . ATS, page 97-102. IEEE Computer Society, (2015)Novel Techniques for Achieving High At-Speed Transition Fault Test Coverage for Motorola's Microprocessors Based on PowerPC(tm) Instruction Set Architecture., , , , , and . VTS, page 3-8. IEEE Computer Society, (2002)The Impacts of Untestable Defects on Transition Fault Testing., and . VTS, page 2-7. IEEE Computer Society, (2006)Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (3): 499-512 (2016)Full Scan Fault Coverage With Partial Scan., , and . DATE, page 468-472. IEEE Computer Society / ACM, (1999)Measures to Improve Delay Fault Testing on Low-Cost Testers - A Case Study., , , , and . VTS, page 223-228. IEEE Computer Society, (2005)Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality., , , , , and . DATE, page 56-61. IEEE Computer Society, (2005)