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Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures.

, , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)

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Processor modeling and code selection for retargetable compilation., , , and . ACM Trans. Design Autom. Electr. Syst., 6 (3): 277-307 (2001)Data routing: a paradigm for efficient data-path synthesis and code generation., , , and . HLSS, page 17-22. ACM, (1994)Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures., , , , , , , , , and . VLSI Signal Processing, 9 (1-2): 49-65 (1995)Instruction set definition and instruction selection for ASIPs., , , and . HLSS, page 11-16. ACM, (1994)Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite., , , and . SoC, page 1-4. IEEE, (2006)Chess: retargetable code generation for embedded DSP processors., , , , , , and . Code Generation for Embedded Processors, page 85-102. Kluwer, (1994)A Graph Based Processor Model for Retargetable Code Generation., , , , and . ED&TC, page 102-107. IEEE Computer Society, (1996)Models for bit-true simulation and high-level synthesis of DSP applications., , , , and . Great Lakes Symposium on VLSI, page 52-59. IEEE, (1992)Open-ended system for high-level synthesis of flexible signal processors., , , , , and . EURO-DAC, page 272-276. IEEE Computer Society, (1990)Efficient microcoded processor design for fixed rate DFT and FFT., , and . VLSI Signal Processing, 1 (4): 287-306 (1990)