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Disambiguation of "Nakatake, Shigetoshi"

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Overview of the 2017 CAD contest at ICCAD: Invited paper.

, , , and . ICCAD, page 855-856. IEEE, (2017)

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Other publications of authors with the same name

Low Voltage CMOS Current Mode Reference Circuit without Operational Amplifiers., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 101-A (5): 748-754 (2018)A Finite Element-Domain Decomposition Coupled Resistance Extraction Method with Virtual Terminal Insertion., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 91-A (2): 542-549 (2008)Consistent floorplanning with hierarchical superconstraints., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (1): 42-49 (2002)On-chip resistance configuration by subthreshold MOSFET-array for ultra weak current sensing., and . APCCAS, page 261-264. IEEE, (2019)Regularity-oriented analog placement with diffusion sharing and well island generation., , , , , , and . ASP-DAC, page 305-311. IEEE, (2010)A Perceptron Circuit with DAC-Based Multiplier for Sensor Analog Front-Ends., , , and . NGCAS, page 93-96. IEEE, (2017)Practicality on placement given by optimality of packing.. ISPD, page 59-60. ACM, (2013)The oct-touched tile: a new architecture for shape-based routing., , , and . ACM Great Lakes Symposium on VLSI, page 126-129. ACM, (2005)Overview of the 2016 CAD contest at ICCAD., , , and . ICCAD, page 38. ACM, (2016)Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts., , , and . ASP-DAC/VLSI Design, page 467-472. IEEE Computer Society, (2002)