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Early load address resolution via register tracking., , , , , and . ISCA, page 306-315. IEEE Computer Society, (2000)Intel Alder Lake CPU Architectures., , , , , , , , , and 2 other author(s). IEEE Micro, 42 (3): 13-19 (2022)Correlated Load-Address Predictors., , , , , , and . ISCA, page 54-63. IEEE Computer Society, (1999)Tango: A Hardware-Based Data Prefetching Technique for Superscalar Processors., and . MICRO, page 214-225. ACM/IEEE Computer Society, (1996)Microarchitectural support for precomputation microthreads., , , and . MICRO, page 74-84. ACM/IEEE Computer Society, (2002)A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification., , , , and . MICRO, page 216-225. ACM/IEEE Computer Society, (1998)Auto-Predication of Critical Branches., , , , , , and . ISCA, page 92-104. IEEE, (2020)Focused Value Prediction., , , , , and . ISCA, page 79-91. IEEE, (2020)Difficult-Path Branch Prediction Using Subordinate Microthreads., , , and . ISCA, page 307-317. IEEE Computer Society, (2002)Speculation Techniques for Improving Load Related Instruction Scheduling., , , and . ISCA, page 42-53. IEEE Computer Society, (1999)