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Dynamic binary translation to a reconfigurable target for on-the-fly acceleration., and . DAC, page 286-287. ACM, (2011)Hardware-efficient on-chip generation of time-extensive constrained-random sequences for in-system validation., , and . DAC, page 121:1-121:6. ACM, (2013)Power-Conscious Test Synthesis and Scheduling., and . IEEE Des. Test Comput., 20 (4): 48-55 (2003)Variable-length input Huffman coding for system-on-a-chip test., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (6): 783-796 (2003)Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 27 (11): 2092-2097 (2008)BIST hardware synthesis for RTL data paths based on testcompatibility classes., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 19 (11): 1375-1385 (2000)Hardware-based parallel computing for real-time haptic rendering of deformable objects., , , , , , , , and . IROS, page 4187. IEEE, (2008)Automated data analysis solutions to silicon debug., , and . DATE, page 982-987. IEEE, (2009)Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns., and . IEEE Trans. Very Large Scale Integr. Syst., 17 (9): 1353-1357 (2009)Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation., and . IEEE Trans. Very Large Scale Integr. Syst., 25 (6): 1866-1880 (2017)