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Disambiguation of "Pulte, Christopher"

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Modelling the ARMv8 architecture, operationally: concurrency and ISA.

, , , , , , , and . POPL, page 608-621. ACM, (2016)

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Josef Pulte

Peter Pulte

Thomas Pulte

Matthias Pulte

Helmut Pulte

 

Other publications of authors with the same name

Isla: Integrating Full-Scale ISA Semantics and Axiomatic Concurrency Models., , , , and . CAV (1), volume 12759 of Lecture Notes in Computer Science, page 303-316. Springer, (2021)Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8., , , , , and . Proc. ACM Program. Lang., 2 (POPL): 19:1-19:29 (2018)Promising-ARM/RISC-V: a simpler and faster operational concurrency model., , , , and . PLDI, page 1-15. ACM, (2019)Relaxed virtual memory in Armv8-A., , , , , and . ESOP, volume 13240 of Lecture Notes in Computer Science, page 143-173. Springer, (2022)Mixed-size concurrency: ARM, POWER, C/C++11, and SC., , , , , , , , and . POPL, page 429-442. ACM, (2017)Modelling the ARMv8 architecture, operationally: concurrency and ISA., , , , , , , and . POPL, page 608-621. ACM, (2016)ARMv8-A System Semantics: Instruction Fetch in Relaxed Architectures., , , , , , and . ESOP, volume 12075 of Lecture Notes in Computer Science, page 626-655. Springer, (2020)Repairing and mechanising the JavaScript relaxed memory model., , , , , , , and . PLDI, page 346-361. ACM, (2020)The semantics of multicopy atomic ARMv8 and RISC-V. University of Cambridge, UK, (2019)British Library, EThOS.