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Disambiguation of "Chen, Liang-Gee"

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Algorithm and implementation of multi-channel spike sorting using GPU in a home-care surveillance system.

, , and . ICME, page 1-6. IEEE Computer Society, (2011)

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Liang Chen

Liang Chen

Liang Chen

Liang-chi Chen

Yen-liang Chen

 

Other publications of authors with the same name

Analysis and Design of On-sensor ECG Processors for Realtime Detection of Cardiac Anomalies Including VF, VT, and PVC., , , , , , , and . J. Signal Process. Syst., 65 (2): 275-285 (2011)A bit-level pipelined VLSI architecture for the running order algorithm., , and . IEEE Trans. Signal Process., 45 (8): 2140-2144 (1997)An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System., , , and . VLSI Signal Processing, 41 (2): 183-191 (2005)VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters., , and . VLSI Signal Processing, 40 (2): 175-188 (2005)Pipeline interleaving design for FIR, IIR, and FFT array processors., , and . VLSI Signal Processing, 10 (3): 275-293 (1995)Automatic threshold decision of background registration technique for video segmentation., , , and . VCIP, volume 4671 of Proceedings of SPIE, page 552-563. SPIE, (2002)The Chip Design of A 32-b Logarithmic Number System., , and . ISCAS, page 167-170. IEEE, (1994)Analysis and design of macroblock pipelining for H.264/AVC VLSI architecture., , and . ISCAS (2), page 273-276. IEEE, (2004)Priority depth fusion for the 2D to 3D conversion system., , , , , and . Three-Dimensional Image Capture and Applications, volume 6805 of SPIE Proceedings, page 680513. SPIE, (2008)A 473 μW wireless 16-channel neural recording SoC with RF energy harvester., , , , and . VLSI-DAT, page 1-4. IEEE, (2018)