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Disambiguation of "Ishizuka, Okihiko"

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On Design of Multiple-Valued Static Random-Access-Memory.

, , and . ISMVL, page 11-17. IEEE Computer Society, (1990)

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Other publications of authors with the same name

Learning Multiple-Valued Logic Networks Based on Back Propagation., , and . ISMVL, page 270-275. IEEE Computer Society, (1995)Wide Input-Range Four-Quadrant Analog Multiplier Using Floating-Gate MOSFET's., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (7): 1759-1765 (2003)VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products., , , , and . ISMVL, page 169-174. IEEE Computer Society, (1997)Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators., , and . ISMVL, page 27-34. IEEE Computer Society, (2001)Algebraic Properties of a Learning Multiple-Valued Logic Network., , , and . ISMVL, page 196-201. IEEE Computer Society, (1993)On Design of Multiple-Valued Static Random-Access-Memory., , and . ISMVL, page 11-17. IEEE Computer Society, (1990)Multiple-Valued Immune Network Model and Its Simulations., , , , and . ISMVL, page 233-240. IEEE Computer Society, (1997)On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements.. IEEE Trans. Computers, 26 (12): 1251-1257 (1977)Down Literal Circuit with Neuron-MOS Transistors and Its Applications., , and . ISMVL, page 180-185. IEEE Computer Society, (1999)Synthesis of Current-Mode Pass Transistor Networks., , , and . ISMVL, page 139-146. IEEE Computer Society, (1991)