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Disambiguation of "Yan, Dan Lei"

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A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS.

, , and . ESSCIRC, page 524-527. IEEE, (2007)

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Lei Lei

Lei Lei

Yan Yan

Lei Zhao

Lei Shi

 

Other publications of authors with the same name

A 35mW, 2.32dB NF, 1.1° Phase Error, 18-21.2GHz Beamforming Receiver IC for Satcom on the Move (SOTM) Phased Arrays., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (10): 3847-3851 (October 2023)A Universal UHF RFID Reader IC in 0.18-µm CMOS Technology., , , , , , , , , and . IEEE J. Solid State Circuits, 43 (5): 1146-1155 (2008)Digital Compensation Method for the Path Delay Mismatches in GRO-TDC., , , and . Journal of Circuits, Systems, and Computers, 25 (1): 1640008:1-1640008:12 (2016)A -121dBm sensitivity, 2μJ/bit Rx, 8.8μJ/bit Tx, narrowband transceiver for ARIB STD and IoT., , , , , and . A-SSCC, page 185-188. IEEE, (2017)Digital compensation method for the path delay mismatches in GRO-TDC., , , and . ISIC, page 75-78. IEEE, (2014)A 29-31-GHz, 0.4-dB Amplitude Error and 1° Phase Error Beamforming IC and 20-dB Dynamic Range Power Detector for SatCom Phased Arrays., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (10): 3837-3841 (October 2023)A 5.1Gb/s 60.3fJ/bit/mm PVT tolerant NoC transceiver., , , , , , and . A-SSCC, page 141-144. IEEE, (2016)A low-power digital design of all digital PLL for 2.4G wireless communication applications., and . ISIC, page 1-4. IEEE, (2016)A 400MHz low power fractional-N synthesizer with GFSK/GMSK modulation in 0.13μm CMOS., , , and . ISIC, page 556-559. IEEE, (2014)A 1.4-psec Jitter 2.5-Gb/s CDR with wide acquisition range in 0.18-μm CMOS., , and . ESSCIRC, page 524-527. IEEE, (2007)