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ChamNet: Towards Efficient Network Design Through Platform-Aware Model Adaptation.

, , , , , , , , , , , , and . CVPR, page 11398-11407. Computer Vision Foundation / IEEE, (2019)

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Heterogeneous and Multi-Level Compression Techniques for Test Volume Reduction in Systems-on-Chip., , , , and . VLSI Design, page 65-70. IEEE Computer Society, (2005)Task Graph Extraction for Embedded System Synthesis., and . VLSI Design, page 480-. IEEE Computer Society, (2003)High-level Synthesis of Multi-process Behavioral Descriptions., , , and . VLSI Design, page 467-473. IEEE Computer Society, (2003)Synthesis of System-on-a-chip for Testability., and . VLSI Design, page 149-156. IEEE Computer Society, (2001)Thermal characterization of BIST, scan design and sequential test methodologies., and . ITC, page 1-9. IEEE Computer Society, (2009): Reducing test application time in high-level test generation., , and . ITC, page 829-838. IEEE Computer Society, (2000)Hardware-Software Co-Design for Test: It's the Last Straw!, , , , , , and . VTS, page 506-507. IEEE Computer Society, (1996)Automated energy/performance macromodeling of embedded software., , , and . DAC, page 99-102. ACM, (2004)An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology., and . DATE, page 974-979. IEEE Computer Society, (2004)CMOS logic design with independent-gate FinFETs., , and . ICCD, page 560-567. IEEE, (2007)