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Optimised Synthesis of Asynchronous Elastic Dataflows by Leveraging Clocked EDA.

, , , and . DSD, page 607-614. IEEE Computer Society, (2014)

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Synthesising Heterogeneously Encoded Systems., , and . ASYNC, page 138-149. IEEE Computer Society, (2006)Prime Indicants: A Synthesis Method for Indicating Combinational Logic Blocks., and . ASYNC, page 139-150. IEEE Computer Society, (2009)Indicating combinational logic decomposition., and . IET Comput. Digit. Tech., 5 (4): 331-341 (2011)Energy Efficient Power-Management for Out-of-Order Processors Using Cyclic Power-Gating., , and . ARCS, volume 12800 of Lecture Notes in Computer Science, page 183-198. Springer, (2021)M-of-N Code Decomposition for Indicating Combinational Logic., and . ASYNC, page 15-25. IEEE Computer Society, (2010)Redundant Logic Insertion and Latency Reduction in Self-Timed Adders., , and . VLSI Design, (2012)Efficient synthesis of speed-independent combinational logic circuits., and . ASP-DAC, page 1022-1026. ACM Press, (2005)Energy-Efficient Encoding for High-Speed Serial Interfaces., , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (10): 1484-1496 (2022)DiAD - Distributed Acceleration for Datacenter FPGAs., , , , , and . FPL, page 166-173. IEEE, (2023)Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes., , , and . ASYNC, page 132-140. IEEE Computer Society, (2003)