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Disambiguation of "Yang, Chih-Kong Ken"

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A Sub-50fs-Jitter Sub-Sampling PLL with a Harmonic-Enhanced 30-GHz-Fundemental Class-C VCO in 0.18µm SiGe BiCMOS.

, , , , , , , and . ESSCIRC, page 435-438. IEEE, (2021)

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Chih-Yun Yang

Chia-Chih Yang

Matei Chihaia

Walid Shehab Chihab

Ken Lau

 

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Effects of Active Cooling on Workload Management in High Performance Processors., and . CLOSER, page 5-16. SciTePress, (2015)An 85%-Efficiency Hybrid DC-DC Converter for Sub-Microwatt IoT Applications., and . MWSCAS, page 9-12. IEEE, (2019)A 4.8 GS/s 5-bit ADC-Based Receiver With Embedded DFE for Signal Equalization., and . IEEE J. Solid State Circuits, 44 (3): 901-915 (2009)A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation., and . IEEE J. Solid State Circuits, 38 (11): 1804-1812 (2003)A 14-bit, 10-Msamples/s D/A converter using multibit ΣΔ modulation., , and . IEEE J. Solid State Circuits, 34 (5): 607-615 (1999)Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference., , , and . IEEE J. Solid State Circuits, 41 (1): 3-6 (2006)CMOS LC oscillator using variable mean frequency., , and . CICC, page 147-150. IEEE, (2003)Device-circuit co-optimization for mixed-mode circuit design via geometric programming., , , and . ICCAD, page 470-475. IEEE Computer Society, (2007)A 4.6GHz MDLL with -46dBc reference spur and aperture position tuning., , , , and . ISSCC, page 466-468. IEEE, (2011)A 600-MS/s 5-bit pipeline A/D converter using digital reference calibration., and . IEEE J. Solid State Circuits, 41 (2): 310-319 (2006)