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Disambiguation of "Yamauchi, Hiroyuki"

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An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's.

, , and . IEEE J. Solid State Circuits, 30 (4): 423-431 (April 1995)

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Hiroyuki Tan

Hiroyuki Kobayashi

Hiroyuki Isobe

Hiroyuki Okamuro

Hiroyuki Takada

 

Other publications of authors with the same name

A Discussion on SRAM Circuit Design Trend in Deeper Nanometer-Scale Technologies.. IEEE Trans. Very Large Scale Integr. Syst., 18 (5): 763-774 (2010)An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory., , , , , , , , , and . IEEE J. Solid State Circuits, 48 (3): 864-877 (2013)Errors in solving inverse problem for reversing RTN effects on VCCmin shift in SRAM reliability screening test designs., and . SoCC, page 318-323. IEEE, (2014)17.3 A 28nm 256kb 6T-SRAM with 280mV improvement in VMIN using a dual-split-control assist scheme., , , , , and . ISSCC, page 1-3. IEEE, (2015)A Method and Language for Constructing Multiagent Systems., and . ISMIS, volume 1932 of Lecture Notes in Computer Science, page 619-628. Springer, (2000)A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme., , , , , , and . IEEE J. Solid State Circuits, 52 (9): 2498-2514 (2017)Ringing error prevention techniques in Lucy-Richardson deconvolution process for SRAM space-time margin variation effect screening designs., and . LATS, page 1-6. IEEE Computer Society, (2015)A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme., , , and . CICC, page 233-236. IEEE, (2007)Convolution/deconvolution SRAM analyses for complex gamma mixtures RTN distributions., and . ICICDT, page 33-36. IEEE, (2013)Deconvolution algorithm dependencies of estimation errors of RTN effects on subnano-scaled SRAM margin variation., and . VLSI-SoC, page 1-6. IEEE, (2014)