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On-chip supply power measurement and waveform reconstruction in a 28nm FD-SOI processor SoC., , , , , , , , и . A-SSCC, стр. 125-128. IEEE, (2016)A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET., , , , , , , , , и . ASYNC, стр. 27-35. IEEE, (2019)Accelerating Chip Design With Machine Learning., , , , , , , , , и 1 other автор(ы). IEEE Micro, 40 (6): 23-32 (2020)A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm., , , , , , , , , и 7 other автор(ы). IEEE J. Solid State Circuits, 55 (4): 920-932 (2020)A Pausible Bisynchronous FIFO for GALS Systems., , и . ASYNC, стр. 1-8. IEEE Computer Society, (2015)A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm., , , , , , , , , и 7 other автор(ы). VLSI Circuits, стр. 300-. IEEE, (2019)MAGNet: A Modular Accelerator Generator for Neural Networks., , , , , , , , , и 6 other автор(ы). ICCAD, стр. 1-8. ACM, (2019)Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC., , , , , , , , , и 4 other автор(ы). ESSCIRC, стр. 269-272. IEEE, (2016)A fast, flexible, positive and negative adaptive body-bias generator in 28nm FDSOI., , , , , и . VLSI Circuits, стр. 1-2. IEEE, (2016)MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification., , , , , и . DATE, стр. 1825-1828. IEEE, (2021)