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Sampling in Thermal Simulation of Processors: Measurement, Characterization, and Evaluation., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (8): 1187-1200 (2013)A design time simulator for computer architects., , and . ISQED, page 164-173. IEEE, (2011)The UCSC Kestrel Parallel Processor., , , , , , , , , and 4 other author(s). IEEE Trans. Parallel Distributed Syst., 16 (1): 80-92 (2005)Estimating design time for system circuits., , , , and . VLSI-SoC, page 60-65. IEEE, (2007)uComplexity: Estimating Processor Design Effort., , and . MICRO, page 209-218. IEEE Computer Society, (2005)Effective Optimistic-Checker Tandem Core Design through Architectural Pruning., and . MICRO, page 236-248. IEEE Computer Society, (2007)SEED: scalable, efficient enforcement of dependences., , and . PACT, page 254-264. ACM, (2006)Fly Spy: Lightweight Localization and Target Tracking for Cooperating Air and Ground Robots., , , and . DARS, page 315-324. Springer, (2000)Characterizing processor thermal behavior., , and . ASPLOS, page 193-204. ACM, (2010)System and Procesor Design Effort Estimation., , and . VLSI-SoC (Selected Papers), volume 291 of IFIP, page 1-21. Springer, (2007)