Author of the publication

Exploiting dynamic transaction queue size in scalable memory systems.

, , and . Soft Comput., 22 (6): 2065-2077 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Regularized Cross-Layer Ladder Network for Intrusion Detection in Industrial Internet of Things., , , , and . IEEE Trans. Ind. Informatics, 19 (2): 1747-1755 (2023)An Evaluation of Page Aggregation Technique on Different DSM Systems., and . ISHPC, volume 1940 of Lecture Notes in Computer Science, page 134-145. Springer, (2000)L2-Cache Hierarchical Organizations for Multi-core Architectures.. ISPA Workshops, volume 4331 of Lecture Notes in Computer Science, page 74-83. Springer, (2006)RAMON: Region-Aware Memory Controller., and . IEEE Trans. Very Large Scale Integr. Syst., 26 (4): 697-710 (2018)A novel secure DV-Hop localization algorithm against wormhole attacks., , , , , and . Telecommun. Syst., 80 (3): 413-430 (2022)An Evolutionary-Based Approach for Low-Complexity Intrusion Detection in Wireless Sensor Networks., , , , and . Wirel. Pers. Commun., 126 (3): 2019-2042 (2022)A DSM Speedup Comparison: TreadMarks, JIAJIA and Nautilus., and . PDPTA, page 1744-1748. CSREA Press, (1999)A Preliminary Proposal of a Complete Environment for Practical DSMs's Evaluation based on Benchmarks's Execution.. HPCS, page 233-236. IEEE Computer Society, (2002)Two Techniques for Improvement the Speedup of Nautilus DSM.. Computación y Sistemas, 4 (2): 166-177 (2000)Insights on memory controller scaling in multi-core embedded systems., and . Int. J. Embed. Syst., 6 (4): 351-361 (2014)