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Quick error detection tests with fast runtimes for effective post-silicon validation and debug.

, , , , and . DATE, page 1168-1173. ACM, (2015)

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Hot Chips 28., and . IEEE Micro, 37 (2): 5-6 (2017)Transforming nanodevices into nanosystems: The N3XT 1, 000X.. LATS, page 6. IEEE, (2016)A Design Diversity Metric and Analysis of Redundant Systems., , and . IEEE Trans. Computers, 51 (5): 498-510 (2002)The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits., , , , , and . JETC, 10 (4): 33:1-33:19 (2014)Hyperdimensional Computing Nanosystem., , , , , , and . CoRR, (2018)Carbon nanotube computer: transforming scientific discoveries into working systems.. ISPD, page 117-118. ACM, (2014)The N3XT Approach to Energy-Efficient Abundant-Data Computing., , , , , , , , , and 1 other author(s). Proc. IEEE, 107 (1): 19-48 (2019)Robust System Design., , , , , , , , , and 4 other author(s). IPSJ Trans. Syst. LSI Des. Methodol., (2011)Cross-layer resilience challenges: Metrics and optimization., , and . DATE, page 1029-1034. IEEE Computer Society, (2010)