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New 3-D CMOS Fabric With Stacked Horizontal Nanowires., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1625-1634 (2019)A New Concept for Computing Using Interconnect Crosstalks., , , , , and . ICRC, page 1-2. IEEE, (2017)Thermal Management in Fine-Grained 3-D Integrated Circuits., , , , and . CoRR, (2018)Crosstalk-Computing-Based Gate-Level Reconfigurable Circuits., , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (8): 1073-1083 (2022)Crosstalk Noise based Configurable Computing: A New Paradigm for Digital Electronics., , , , and . CoRR, (2020)Fine-grained 3-D CMOS concept using stacked horizontal nanowire., , and . NANOARCH, page 151-152. ACM, (2016)Thermal management challenges and mitigation techniques for transistor-level 3-D integration., , , , and . Microelectron. J., (2019)A Logic Simplification Approach for Very Large Scale Crosstalk Circuit Designs., , , and . CoRR, (2019)On circuit developments to enable large scale circuit design while computing with noise., , , and . Integr., (2022)Crosstalk based Fine-Grained Reconfiguration Techniques for Polymorphic Circuits., , , , , and . NANOARCH, page 114-120. ACM, (2018)