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Efficient architectural exploration of TAGE branch predictor for embedded processors.

, , , , , and . Microelectron. J., (2019)

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Modeling and Analyzing of 3D DRAM as L3 Cache Based on DRAMSim2., , , and . NCCET, volume 592 of Communications in Computer and Information Science, page 3-12. Springer, (2015)Memory Bandwidth and Energy Efficiency Optimization of Deep Convolutional Neural Network Accelerators., , , , and . ACA, volume 908 of Communications in Computer and Information Science, page 15-29. Springer, (2018)Fast FPGA system for microarchitecture optimization on synthesizable modern processor design., , , , , and . FPL, page 1-4. IEEE, (2015)Bandwidth allocation design to guarantee qos of differentiated services for a novel OFDMA-PON., , , , , , and . APCC, page 775-780. IEEE, (2012)BPSim: An integrated missrate, area, and power simulator for branch predictor., , and . MOCAST, page 1-4. IEEE, (2017)Research of Configurable Hybrid Memory Architecture for Big Data Processing., , , , and . NCCET, volume 600 of Communications in Computer and Information Science, page 116-132. Springer, (2017)Design Space Exploration of TAGE Branch Predictor with Ultra-Small RAM., , , , and . ACM Great Lakes Symposium on VLSI, page 281-286. ACM, (2017)Configuration of the Galaxy Grid Node Environment., , , , , , and . GCC Workshops, volume 3252 of Lecture Notes in Computer Science, page 697-703. Springer, (2004)Bidirectional generative transductive zero-shot learning., , , , , and . Neural Comput. Appl., 33 (10): 5313-5326 (2021)Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors., , , , and . ACM Trans. Archit. Code Optim., 10 (3): 18:1-18:25 (2013)