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Disambiguation of "Julien, Franck"

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Dynamic current reduction of CMOS digital circuits through design and process optimization.

, , , , , , , , , , and . PATMOS, page 77-81. IEEE, (2015)

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Julien Köhrle

Julien Bonnamour

Julien Ndinga

Julien Coignet

Julien Bernard

 

Other publications of authors with the same name

Matching degradation of threshold voltage and gate voltage of NMOSFET after Hot Carrier Injection stress., , , , , , , and . Microelectron. Reliab., 51 (9-11): 1561-1563 (2011)Digital-to-analog converters to benchmark the matching performance of a new zero-cost transistor., , , , , , , and . ISCAS, page 761-764. IEEE, (2022)A Schmitt trigger to benchmark the performance of a new zero-cost transistor., , , , , , , , and . ICECS 2022, page 1-4. IEEE, (2022)Dynamic current reduction of CMOS digital circuits through design and process optimization., , , , , , , , , and 1 other author(s). PATMOS, page 77-81. IEEE, (2015)Circuit-level evaluation of a new zero-cost transistor in an embedded non-volatile memory CMOS technology., , , , , , , , , and 1 other author(s). DTIS, page 1-5. IEEE, (2021)Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology., , , , , , , , , and 2 other author(s). MWSCAS, page 897-900. IEEE, (2014)Temperature and hump effect impact on output voltage spread of low power bandgap designed in the sub-threshold area., , , , , , and . ISCAS, page 2549-2552. IEEE, (2011)Layout optimizations to decrease internal power and area in digital CMOS standard cells., , , , , , , , and . MIPRO, page 1582-1587. IEEE, (2015)