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Disambiguation of "Ayala, Javier"

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45nm CMOS - Silicon Photonics Monolithic Technology (45CLO) for Next-Generation, Low Power and High Speed Optical Interconnects.

, , , , , , , , , , , , , , , , , , , , , and . OFC, page 1-3. IEEE, (2020)

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Manuela Ayala Jurado

Virginia Carolina Ayala

Mauricio Ayala-Rincón

Fidel Ayala Guardia

Melvin Ayala

 

Other publications of authors with the same name

A CMOS Compatible Monolithic Fiber Attach Solution with Reliable Performance and Self-Alignment., , , , , , , , , and 16 other author(s). OFC, page 1-3. IEEE, (2020)Monolithically integrated silicon nitride platform., , , , , , , , , and 39 other author(s). OFC, page 1-3. IEEE, (2021)FEC-Free 60-Gb/s Silicon Photonic Link Using SiGe-Driver ICs Hybrid-Integrated with Photonics-Enabled CMOS., , , , , , , , , and 1 other author(s). OFC, page 1-3. IEEE, (2018)High Performance Avalanche Photodiode in a Monolithic Silicon Photonics Technology., , , , , , , , , and 21 other author(s). OFC, page 1-3. IEEE, (2022)45nm CMOS - Silicon Photonics Monolithic Technology (45CLO) for Next-Generation, Low Power and High Speed Optical Interconnects., , , , , , , , , and 12 other author(s). OFC, page 1-3. IEEE, (2020)From 2D to 3D: Teaching terrain representation in engineering studies through Augmented reality: Comparative versus 3D pdf., , and . FIE, page 1-4. IEEE Computer Society, (2014)Incorporation of 3D ICT elements into class., , and . Comput. Appl. Eng. Educ., 25 (3): 542-549 (2017)Improving graphic expression training with 3D models., , and . J. Vis., 20 (4): 889-904 (2017)