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On High-Bandwidth Data Cache Design for Multi-Issue Processors.

, , , and . MICRO, page 46-56. ACM/IEEE Computer Society, (1997)

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Power management of multi-core chips: Challenges and pitfalls., , , , , , , , , and 1 other author(s). DATE, page 977-982. IEEE, (2012)Online Estimation of Architectural Vulnerability Factor for Soft Errors., , , and . ISCA, page 341-352. IEEE Computer Society, (2008)Reducing instruction fetch energy with backwards branch control information and buffering., , , and . ISLPED, page 322-325. ACM, (2003)Performance aspects of high-bandwidth multi-lateral cache organizations.. University of Michigan, USA, (1998)The Case for Lifetime Reliability-Aware Microprocessors., , , and . ISCA, page 276-287. IEEE Computer Society, (2004)Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory., , , and . ICCD, page 366-372. IEEE Computer Society, (2011)SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors., , , and . DSN, page 496-505. IEEE Computer Society, (2005)Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions., , , and . DSN, page 266-275. IEEE Computer Society, (2007)On High-Bandwidth Data Cache Design for Multi-Issue Processors., , , and . MICRO, page 46-56. ACM/IEEE Computer Society, (1997)SDCTune: A model for predicting the SDC proneness of an application for configurable protection., , , and . CASES, page 23:1-23:10. ACM, (2014)