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Disambiguation of "Jan, Mathieu"

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Exploration of Fault Effects on Formal RISC-V Microarchitecture Models.

, , , , and . FDTC, page 73-83. IEEE, (2022)

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Mathieu Jan

Herbert Mathieu

Herbert Mathieu

Mathieu Mathias

Theodor Mathieu

 

Other publications of authors with the same name

The Role of Causality in a Formal Definition of Timing Anomalies., , , , and . RTCSA, page 91-102. IEEE, (2022)Shedding the Shackles of Time-Division Multiplexing., , , and . RTSS, page 456-468. IEEE Computer Society, (2018)μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections., , , , and . FMCAD, page 101-109. IEEE, (2023)Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code., , , and . RTAS, page 305-308. IEEE, (2022)Towards Formal Co-validation of Hardware and Software Timing Models of CPSs., , , , and . CyPhy/WESE, volume 11971 of Lecture Notes in Computer Science, page 203-227. Springer, (2019)Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults., , , , , , , , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024 (4): 179-204 (2024)Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs., , , and . MEMOCODE, page 1-8. IEEE, (2022)Exploration of Fault Effects on Formal RISC-V Microarchitecture Models., , , , and . FDTC, page 73-83. IEEE, (2022)Formal Semantics of Predictable Pipelines: a Comparative Study., , , and . ASP-DAC, page 103-108. IEEE, (2020)A memory interference analysis using a formal timing analyzer (WIP)., , , , and . LCTES, page 146-150. ACM, (2022)