( en | de | ru )

 

Disambiguation

From post

копироватьудалитьдобавить публикацию в буфер
Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map Reconfiguration.

, , , и . IEEE Trans. Parallel Distributed Syst., 29 (9): 2105-2120 (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

Shaojun Lu

Shaojun Tong

Wei Wei

Wei Wei

Wei Wei

 

Другие публикации лиц с тем же именем

LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGA., , , , , и . DAC, стр. 16:1-16:6. ACM, (2018)An efficient kernel transformation architecture for binary- and ternary-weight neural network inference., , , , и . DAC, стр. 137:1-137:6. ACM, (2018)A 2.69 Mbps/mW 1.09 Mbps/kGE Conjugate Gradient-based MMSE Detector for 64-QAM 128×8 Massive MIMO Systems., , , , , и . A-SSCC, стр. 191-194. IEEE, (2018)A Multi-Modal Face Recognition Method Using Complete Local Derivative Patterns and Depth Maps., , , , и . Sensors, 14 (10): 19561-19581 (2014)Aggressive Pipelining of Irregular Applications on Reconfigurable Hardware., , , , , и . ISCA, стр. 575-586. ACM, (2017)Data cache prefetching via context directed pattern matching for coarse-grained reconfigurable arrays., , , и . DAC, стр. 64:1-64:6. ACM, (2016)Polyhedral model based mapping optimization of loop nests for CGRAs., , , и . DAC, стр. 19:1-19:8. ACM, (2013)Energy-aware loops mapping on multi-vdd CGRAs without performance degradation., , , и . ASP-DAC, стр. 312-317. IEEE, (2017)AEPE: An area and power efficient RRAM crossbar-based accelerator for deep CNNs., , , , , , , , , и . NVMSA, стр. 1-6. IEEE, (2017)Memory fartitioning-based modulo scheduling for high-level synthesis., , , , , и . ISCAS, стр. 1-4. IEEE, (2017)