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ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement., , , and . ISPD, page 157-164. ACM, (2015)Lagrangian Relaxation Based Gate Sizing With Clock Skew Scheduling - A Fast and Effective Approach., , and . ISPD, page 129-137. ACM, (2019)Design Optimization by Fine-grained Interleaving of Local Netlist Transformations in Lagrangian Relaxation., , , , and . ISPD, page 87-94. ACM, (2020)Session details: Detailed Routing Contest Results.. ISPD, ACM, (2019)Rapid gate sizing with fewer iterations of Lagrangian Relaxation., , , and . ICCAD, page 337-343. IEEE, (2017)Closing the power gap between ASIC and custom: an ASIC perspective., and . DAC, page 275-280. ACM, (2005)Achieving 550Mhz in an ASIC Methodology., , and . DAC, page 420-425. ACM, (2001)ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement., , , , and . ISPD, page 161-168. ACM, (2014)Fast Lagrangian Relaxation Based Gate Sizing using Multi-Threading., , , and . ICCAD, page 426-433. IEEE, (2015)Fast Lagrangian Relaxation-Based Multithreaded Gate Sizing Using Simple Timing Calibrations., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (7): 1456-1469 (2020)