Author of the publication

A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction.

, , and . ISCAS, page 177-180. IEEE, (2000)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Analysis and Design of Open-Loop Multiphase Local-Oscillator Generator for Wireless Applications., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (5): 970-981 (2010)Analysis and Modeling of a Gain-Boosted N-Path Switched-Capacitor Bandpass Filter., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (9): 2560-2568 (2014)Gain Error Calibrations for Two-Step ADCs: Optimizations Either in Accuracy or Chip Area., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (11): 2279-2289 (2018)A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques., , , and . IEEE J. Solid State Circuits, 54 (12): 3396-3409 (2019)A Reconfigurable Cross-Connected Wireless-Power Transceiver for Bidirectional Device-to-Device Wireless Charging., , and . IEEE J. Solid State Circuits, 54 (9): 2579-2589 (2019)A 0.044-mm2 0.5-to-7-GHz Resistor-Plus-Source-Follower-Feedback Noise-Cancelling LNA Achieving a Flat NF of 3.3±0.45 dB., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 71-75 (2019)A 0.19 mm2 10 b 2.3 GS/s 12-Way Time-Interleaved Pipelined-SAR ADC in 65-nm CMOS., , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3606-3616 (2018)A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 66-I (12): 4850-4861 (2019)Experimental 1-V flexible-IF CMOS analoguebaseband chain for IEEE 802.11a/b/g WLAN receivers., , and . IET Circuits Devices Syst., 1 (6): 415-426 (2007)A 0.4 V 6.4 μW 3.3 MHz CMOS Bootstrapped Relaxation Oscillator with ±0.71% Frequency Deviation over -30 to 100 °C for Wearable and Sensing Applications., , and . ISCAS, page 1-5. IEEE, (2018)