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Disambiguation of "Venkatesha, M. K."

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Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit.

, , , , and . CoRR, (2013)

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K M Heinroth

Marcus K M Tso

Otmar M K Klag

Christian-Thalès Mutale K -M

Aman K K Bhasin

 

Other publications of authors with the same name

A Novel Approach for Authentication of Online Handwritten Signature Based on residuals, poles and zeros., , and . IJPRAI, 25 (1): 57-81 (2011)Signature authentication based on subpattern analysis., , and . Appl. Soft Comput., 11 (3): 3218-3228 (2011)Multi-modal Authentication Using Continuous Dynamic Programming., , , and . COST 2101/2102 Conference, volume 5707 of Lecture Notes in Computer Science, page 228-235. Springer, (2009)Optimized reversible BCD adder using new reversible logic gates, and . CoRR, (2010)Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit., , , , and . CoRR, (2013)An approach for on-line signature authentication using Zernike moments., , and . Pattern Recognit. Lett., 32 (5): 749-760 (2011)A Low-Power Low-Voltage CMOS Thyristor Based Delay Element., , and . ICETET, page 135-140. IEEE Computer Society, (2009)Signature and Iris Authentication Based on Derived Kinematic Values., , , and . IJPRAI, 24 (8): 1237-1260 (2010)Revisiting feature level and score level fusion techniques in multimodal biometrics system., , and . ICMCS, page 881-885. IEEE, (2012)Preface., , and . J. Glob. Optim., 40 (1-3): 1-5 (2008)