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Disambiguation of "Bahar, R. Iris"

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Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits.

, , , , and . DATE, page 576-581. EDA Consortium, San Jose, CA, USA, (2007)

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Bahar Haghanipour

Kayvan Baharmast

Cengiz Iristay

Aida Baharuddin

Bahar Hadzaad

Genexpressionen der Cytochrome P450 1B1 und 2E1 in Abhängigkeit einer PAH-Einwirkung infolge Rauchens sowie der individuellen Suszeptibilität. Uni Gießen, (2009)
 

Other publications of authors with the same name

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits., , , and . DATE, page 1-6. European Design and Automation Association, (2014)Understanding the Impact of Precision Quantization on the Accuracy and Energy of Neural Networks., , , , and . CoRR, (2016)CMOS dynamic power estimation based on collapsible current source transistor modeling., , , , , and . ISLPD, page 111-116. ACM, (1995)SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs., , , , , , and . CODES+ISSS, page 39-48. ACM, (2011)Architectures for Silicon Nanoelectronics and Beyond., , , , , , , and . Computer, 40 (1): 25-33 (2007)Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (11): 1608-1620 (2010)Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (10): 1101-1115 (1997)Hardware acceleration of feature detection and description algorithms on low-power embedded platforms., , , , and . FPL, page 1-9. IEEE, (2016)Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators., , , and . ACM Trans. Reconfigurable Technol. Syst., 7 (1): 4:1-4:22 (2014)Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack., , , , , , and . J. Electron. Test., 35 (6): 887-900 (2019)