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Disambiguation of "Eyerman, Stijn"

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Projecting Performance for PIUMA using Down-Scaled Simulation.

, , , , and . HPEC, page 1-7. IEEE, (2020)

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Stijn Cleemput

 

Other publications of authors with the same name

DRAM Bandwidth and Latency Stacks: Visualizing DRAM Bottlenecks., , and . ISPASS, page 322-331. IEEE, (2022)Scale-Model Architectural Simulation., , , , and . ISPASS, page 58-68. IEEE, (2022)Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware., , and . ISPASS, page 216-226. IEEE Computer Society, (2011)Restating the Case for Weighted-IPC Metrics to Evaluate Multiprogram Workload Performance., and . IEEE Comput. Archit. Lett., 13 (2): 93-96 (2014)Bottle graphs: visualizing scalability bottlenecks in multi-threaded applications., , , and . OOPSLA, page 355-372. ACM, (2013)Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions., , , and . MICRO, page 767-778. ACM, (2021)Studying Compiler-Microarchitecture Interactions through Interval Analysis., , and . PACT, page 406. IEEE Computer Society, (2007)Symbiotic job scheduling on the IBM POWER8., , , and . HPCA, page 669-680. IEEE Computer Society, (2016)Characterizing the branch misprediction penalty., , and . ISPASS, page 48-58. IEEE Computer Society, (2006)Micro-architecture independent analytical processor performance and power modeling., , , , , , , and . ISPASS, page 32-41. IEEE Computer Society, (2015)