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An Approach to Parallelize Kruskal's Algorithm Using Helper Threads.

, , , and . IPDPS Workshops, page 1601-1610. IEEE Computer Society, (2012)

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Facilitating efficient synchronization of asymmetric threads on hyper-threaded processors., and . IPDPS, page 1-8. IEEE, (2008)Early experiences on accelerating Dijkstra's algorithm using transactional memory., , , and . IPDPS, page 1-8. IEEE, (2009)Exploring the performance limits of simultaneous multithreading for memory intensive applications., , , and . J. Supercomput., 44 (1): 64-97 (2008)Performance evaluation of the sparse matrix-vector multiplication on modern architectures., , , , and . J. Supercomput., 50 (1): 36-77 (2009)PLQCD library for Lattice QCD on multi-core machines., , , , , and . CoRR, (2014)LCA: a memory link and cache-aware co-scheduling approach for CMPs., , , , , and . PACT, page 469-470. ACM, (2014)Exploring the Capacity of a Modern SMT Architecture to Deliver High Scientific Application Performance., , , and . HPCC, volume 4208 of Lecture Notes in Computer Science, page 180-189. Springer, (2006)Forecasting Resource Demand for Dynamic Datacenter Sizing in Telco Infrastructures., , , , , , , and . IEEE Big Data, page 3813-3822. IEEE, (2023)Exploring the Performance Limits of Simultaneous Multithreading for Scientific Codes., , , and . ICPP, page 45-54. IEEE Computer Society, (2006)Tuning Blocked Array Layouts to Exploit Memory Hierarchy in SMT Architectures., , , and . Panhellenic Conference on Informatics, volume 3746 of Lecture Notes in Computer Science, page 600-610. Springer, (2005)