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Disambiguation of "Ramakrishnan, Venkatraman"

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Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort.

, , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (8): 2657-2663 (2023)

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Dheera Venkatraman

Rishi Ramakrishnan

Muniarajan Ramakrishnan

Chinnaswamy Ramakrishnan

Ayyappan Ramakrishnan

 

Other publications of authors with the same name

A Silicon Testing Strategy for Pulse-Width Failures., , , , and . VLSI Design, page 352-357. IEEE Computer Society, (2012)Placement aware clock gate cloning and redistribution methodology., , and . ISQED, page 432-436. IEEE, (2012)Beyond SPICE Simulation: A Novel Variability-Aware STA Methodology for Digital Timing Closure., , , , , , , , , and 2 other author(s). SMACD, page 1-4. IEEE, (2023)Ensuring On-Die Power Supply Robustness in High-Performance Designs., , , , , and . VLSI Design, page 220-225. IEEE Computer Society, (2011)DFM: Impact analysis in a high performance design., , , and . ISQED, page 110-115. IEEE, (2011)Aging-Aware Timing Model of CMOS Inverter: Path Level Timing Performance and Its Impact on the Logical Effort., , , , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (8): 2657-2663 (2023)Variation Aware Timing Model of CMOS Inverter for an Efficient ECSM Characterization., , , , , and . ISQED, page 251-256. IEEE, (2021)Early clock prototyping for design analysis and quality entitlement., , and . ISQED, page 641-646. IEEE Computer Society, (2009)Dynamic Co-Simulation Methods for Combined Transmission-Distribution System and Integration Time Step Impact on Convergence., , and . CoRR, (2018)An Approach to Measure the Performance Impact of Dynamic Voltage Fluctuations Using Static Timing Analysis., , , and . VLSI Design, page 519-524. IEEE Computer Society, (2009)