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Disambiguation of "Gupta, Rajesh K."

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System Level Online Power Management Algorithms.

, and . DATE, page 606-611. IEEE Computer Society / ACM, (2000)

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Varun K Gupta

Rajesh Saiju

Hybrid Power System Modelling - Simulation and Energy Management Unit Development. Uni Kassel, (2008)

Rajesh Chitta

Rajesh Saiju

Rajesh Narasimha

 

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The Celerity Open-Source 511-Core RISC-V Tiered Accelerator Fabric: Fast Architectures and Design Methodologies for Fast Chips., , , , , , , , , and 10 other author(s). IEEE Micro, 38 (2): 30-41 (2018)Underdesigned and Opportunistic Computing in Presence of Hardware Variability., , , , , , , , , and 2 other author(s). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (1): 8-23 (2013)ACES - Automatic Configuration of Energy Harvesting Sensors with Reinforcement Learning., , , and . CoRR, (2019)Test and fault-tolerance issues in pipelined DSP hardware., and . Digit. Signal Process., 1 (3): 134-144 (1991)TARNet: Task-Aware Reconstruction for Time-Series Transformer., , , , and . KDD, page 212-220. ACM, (2022)Navigating Alignment for Non-identical Client Class Sets: A Label Name-Anchored Federated Learning Framework., , , , , and . KDD, page 3297-3308. ACM, (2023)A Verification Approach for GALS Integration of Synchronous Components., , , , and . FMGALS@MEMOCODE, volume 146 of Electronic Notes in Theoretical Computer Science, page 105-131. Elsevier, (2005)Verification synergies.. IEEE Des. Test Comput., 21 (6): 457 (2004)Faster maximum and minimum mean cycle algorithms for system-performance analysis., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 17 (10): 889-899 (1998)BALBOA: a component-based design environment for system models., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (12): 1597-1612 (2003)