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Disambiguation of "Goudarzi, Maziar"

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Server Consolidation Techniques in Virtualized Data Centers: A Survey.

, and . IEEE Syst. J., 11 (2): 772-783 (2017)

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To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Mehdi Goudarzi

Maziar Mir

Maziar Jafroodi

Maziar Chavoshzadeh

Dahmun Goudarzi

 

Other publications of authors with the same name

Instruction cache leakage reduction by changing register operands and using asymmetric sram cells., and . ACM Great Lakes Symposium on VLSI, page 383-386. ACM, (2008)Temperature-Aware Configurable Cache to Reduce Energy in Embedded Systems., , , and . IEICE Trans. Electron., 91-C (4): 418-431 (2008)SAIR: significance-aware approach to improve QoR of big data processing in case of budget constraint., and . J. Supercomput., 75 (9): 5760-5781 (2019)Simultaneous hardware and time redundancy with online task scheduling for low energy highly reliable standby-sparing system., , , and . ACM Trans. Embed. Comput. Syst., 13 (4): 86:1-86:31 (2014)A Task-Based Greedy Scheduling Algorithm for Minimizing Energy of MapReduce Jobs., and . J. Grid Comput., 16 (4): 535-551 (2018)Data locality and VM interference aware mitigation of data skew in hadoop leveraging modern portfolio theory., and . SAC, page 175-182. ACM, (2018)Gapprox: using Gallup approach for approximation in Big Data processing., , and . J. Big Data, (2019)SRAM Leakage Reduction by Row/Column Redundancy Under Random Within-Die Delay Variation., and . IEEE Trans. Very Large Scale Integr. Syst., 18 (12): 1660-1671 (2010)Dynamically adaptive register file architecture for energy reduction in embedded processors., , and . Microprocess. Microsystems, 39 (2): 49-63 (2015)Power-yield optimization in MPSoC task scheduling under process variation., , and . ISQED, page 747-754. IEEE, (2010)