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Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool.

, , , , and . HEART, page 8:1-8:6. ACM, (2017)

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Hardware Acceleration with Multi-Threading of Java-Based High Level Synthesis Tool., , , , and . HEART, page 8:1-8:6. ACM, (2017)CODIE: Continuation-Based Overlapping Data-Transfers with Instruction Execution., , , and . ICNC, page 71-77. IEEE Computer Society, (2010)Smart Core System for Dependable Many-Core Processor with Multifunction Routers., , , and . ICNC, page 133-139. IEEE Computer Society, (2010)An Implementation of Handshake Join on FPGA., , , and . ICNC, page 95-104. IEEE Computer Society, (2011)A Fully Pipelined Architecture of Quantum-Classical Interface for Realizing Fault-Tolerant Quantum Computer., , , , , , , and . QCE, page 322-323. IEEE, (2023)A state vector quantum simulator working on FPGAs with extensible SATA storage., , , , and . ICFPT, page 272-273. IEEE, (2023)Parallel Matrix-Matrix Multiplication Based on HPL with a GPU-Accelerated PC Cluster., , , , , and . ICNC, page 243-248. IEEE Computer Society, (2010)An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA., , , , , and . CANDAR, page 112-121. IEEE Computer Society, (2013)Triple Line-Based Playout for Go - An Accelerator for Monte Carlo Go., , , , , and . ReConFig, page 161-166. IEEE Computer Society, (2009)A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine., , , and . FPL, page 490-495. IEEE Computer Society, (2011)