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End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform., , , , , , , , , and 1 other author(s). CoRR, (2022)De-RISC: A Complete RISC-V Based Space-Grade Platform., , , , , , , , , and 5 other author(s). DATE, page 802-807. IEEE, (2022)SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation., , , , , , , , , and . IOLTS, page 1-7. IEEE, (2021)An Academic RISC-V Silicon Implementation Based on Open-Source Components., , , , , , , , , and 24 other author(s). DCIS, page 1-6. IEEE, (2020)SafeSU: an Extended Statistics Unit for Multicore Timing Interference., , , , , , , and . ETS, page 1-4. IEEE, (2021)SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks., , , , , , , and . CoRR, (2022)SafeDE: a flexible Diversity Enforcement hardware module for light-lockstepping., , , , , , , , and . IOLTS, page 1-7. IEEE, (2021)SafeX: Open Source Hardware and Software Components for Safety-Critical Systems., , , , , , , , and . FDL, page 1-4. IEEE, (2022)DVINO: A RISC-V Vector Processor Implemented in 65nm Technology., , , , , , , , , and 33 other author(s). DCIS, page 1-6. IEEE, (2022)SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores., , , , , and . DATE, page 358-363. IEEE, (2022)