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Disambiguation of "Tsukude, Masaki"

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Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters.

, , , , , , and . IEEE Des. Test Comput., 10 (2): 6-12 (1993)

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Masaki Nakajima

 

Other publications of authors with the same name

A New Array Architecture for Parallel Testing in VLSI Memories., , , , and . ITC, page 322-326. IEEE Computer Society, (1989)High-speed/high-bandwidth design methodologies for on-chip DRAM core multimedia system LSI's., , , , , and . IEEE J. Solid State Circuits, 32 (3): 477-482 (1997)A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme., , , and . IEEE J. Solid State Circuits, 32 (11): 1721-1727 (1997)400-MHz random column operating SDRAM techniques with self-skew compensation., , , , , , and . IEEE J. Solid State Circuits, 33 (5): 770-778 (1998)Highly Reliable Testing of ULSI Memories with On-Chip Voltage-Down Converters., , , , , , and . IEEE Des. Test Comput., 10 (2): 6-12 (1993)An experimental 256-Mb DRAM with boosted sense-ground scheme., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 29 (11): 1303-1309 (November 1994)A 1.6-GB/s data-rate 1-Gb synchronous DRAM with hierarchical square-shaped memory block and distributed bank architecture., , , , , , , , , and 3 other author(s). IEEE J. Solid State Circuits, 31 (11): 1645-1655 (1996)SOI-DRAM circuit technologies for low power high speed multigiga scale memories., , , , , , and . IEEE J. Solid State Circuits, 31 (4): 586-591 (1996)Low voltage circuit design techniques for battery-operated and/or giga-scale DRAMs., , , , , and . IEEE J. Solid State Circuits, 30 (11): 1183-1188 (November 1995)A Testing Technique for ULSI Memory with On-Chip Voltage Down Converter., , , , , , and . ITC, page 615-622. IEEE Computer Society, (1992)