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Disambiguation of "Nagata, Makoto"

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Accurate analysis of substrate sensitivity of active transistors in an analog circuit.

, , , , , , , , and . ISQED, page 56-61. IEEE, (2011)

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Momoko Nagata

Sabine Nagata

Makoto Yamamoto

Makoto Nakamura

Makoto Arai

 

Other publications of authors with the same name

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation., , , and . CICC, page 849-852. IEEE, (2007)An On-Chip Multichannel Waveform Monitor for Diagnosis of Systems-on-a-Chip Integration., and . IEEE Trans. Very Large Scale Integr. Syst., 15 (10): 1101-1110 (2007)In-Place Signal and Power Noise Waveform Capturing Within 3-D Chip Stacking., , and . IEEE Des. Test, 32 (6): 87-98 (2015)High-Speed Digital Circuit Design Using Differential Logic with Asymmetric Signal Transition., , and . IEICE Trans. Electron., 88-C (10): 2001-2008 (2005)Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 96-A (12): 2516-2523 (2013)Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation., , , and . Proc. IEEE, 94 (12): 2109-2138 (2006)Measurements and Simulation of Sensitivity of Differential-Pair Transistors against Substrate Voltage Variation., , , , , , , , and . IEICE Trans. Electron., 96-C (6): 884-893 (2013)Session 20 overview: Energy harvesting and SC power conversion: Analog subcommittee., and . ISSCC, page 356-357. IEEE, (2015)On-Chip Multi-Channel Monitoring for Analog Circuit Diagnosis in Systems-on-Chip Integration., , and . IEICE Trans. Electron., 90-C (6): 1189-1196 (2007)Co-simulation of On-Chip and On-Board AC Power Noise of CMOS Digital Circuits., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 95-A (12): 2284-2291 (2012)