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Disambiguation of "Tsukamoto, Yasumasa"

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A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline.

, , , , , , , and . VLSIC, page 1-2. IEEE, (2014)

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Masaji Tsukamoto

Masaaki Tsukamoto

Nobuko Ohashi Tsukamoto

 

Other publications of authors with the same name

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure., , , , , and . CICC, page 1-4. IEEE, (2013)A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 43 (1): 96-108 (2008)A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 43 (1): 180-191 (2008)NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator., , , , and . A-SSCC, page 201-204. IEEE, (2017)An Analysis of Local BTI Variation with Ring-Oscillator in Advanced Processes and Its Impact on Logic Circuit and SRAM., , , , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 104-A (11): 1536-1545 (2021)A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry., , , , , , , , , and . A-SSCC, page 17-20. IEEE, (2016)A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues., , , , , , and . IEEE J. Solid State Circuits, 46 (11): 2535-2544 (2011)Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application., , , , , and . ISQED, page 270-274. IEEE, (2012)A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs., , , , , , , and . ISSCC, page 236-238. IEEE, (2012)A dynamic body-biased SRAM with asymmetric halo implant MOSFETs., , , , , , and . ISLPED, page 285-290. IEEE/ACM, (2011)