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Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors.

, , , , , , and . DAC, page 89-94. ACM Press, (1997)

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Simulation of IBM Enterprise System/9000 Models 820 and 900., , , , , , , and . IBM J. Res. Dev., 36 (4): 751-764 (1992)Teaching Future Verification Engineers: The Forgotten Side of Logic Design., , , , , and . DAC, page 253-255. ACM, (2001)Designer-level verification using TIMEDIAG/GENRAND.. IBM J. Res. Dev., 41 (4&5): 581-592 (1997)Functional verification of the CMOS S/390 Parallel Enterprise Server G4 system., , , , , , , , , and 3 other author(s). IBM J. Res. Dev., 41 (4&5): 549-566 (1997)A 4.1-ns compact 54×54-b multiplier utilizing sign-select Booth encoders., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 32 (11): 1676-1682 (1997)Comprehensive Functional Verification: The Complete Industry Cycle, , and . Elsevier, San Diego, CA, (2005)Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system., , , , , , , , , and 15 other author(s). IBM J. Res. Dev., 46 (1): 53-76 (2002)Hierarchical Random Simulation Approach for the Verification of S/390 CMOS Multiprocessors., , , , , , and . DAC, page 89-94. ACM Press, (1997)