Author of the publication

Hardware support for performance measurements and energy estimation of OpenRISC processor.

, , and . SACI, page 399-404. IEEE, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Layered LDPC decoder in-order message access scheduling: a case study., and . SACI, page 193-198. IEEE, (2020)An FPGA sliding window-based architecture harris corner detector., , and . FPL, page 1-4. IEEE, (2014)Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment., , , , and . DSD, page 634-640. IEEE Computer Society, (2007)Quantum circuit's reliability assessment with VHDL-based simulated fault injection., , , and . Microelectron. Reliab., 50 (2): 304-311 (2010)Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding., , and . DSD, page 104-109. IEEE Computer Society, (2018)Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques., , and . DDECS, page 149-152. IEEE Computer Society, (2015)Variable throughput LDPC decoders using SIMD-based adaptive quantization., , , and . TSP, page 425-428. IEEE, (2016)Analysis and implementation of on-the-fly stopping criteria for layered QC LDPC decoders., , , , , , and . MIXDES, page 287-291. IEEE, (2015)Design for dependability in emerging technologies., , , and . JETC, 3 (2): 6 (2007)Configurable FPGA architecture for hardware-software merge sorting., , and . MIXDES, page 179-182. IEEE, (2016)