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An Implementation of the SSF Scalable Simulation Framework on the Cray MTA.

, , , and . PADS, page 77-88. IEEE Computer Society, (2003)

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Design and Implementation of the UW Illustrated Compiler., , and . PLDI, page 105-114. ACM, (1988)The University of Washington Illustrating Compiler., , and . PLDI, page 223-233. ACM, (1990)Phase-Lock Loop Characteristics in the Presence of Nonwhite Noise for Bandpass Types of Modulating Spectra., and . IEEE Trans. Commun., 24 (1): 98-106 (1976)Experience with a Graham-Glanville style code generator., , , , and . SIGPLAN Symposium on Compiler Construction, page 13-24. ACM, (1984)Integrating Register Allocation and Instruction Scheduling for RISCs., , and . ASPLOS, page 122-131. ACM Press, (1991)SIGARCH Computer Architecture News 19(2), SIGOPS Operating System Review 25(Special Issue April 1991), and SIGPLAN Notices 26(4).The Effect on RISC Performance of Register Set Size and Structure Versus Code Generation Strategy., , and . ISCA, page 330-339. ACM, (1991)A multicast ATM switch with slotted ring fabric.. ICCCN, page 500-503. IEEE Computer Society, (1997)The Marion System for Retargetable Instruction Scheduling., , and . PLDI, page 229-240. ACM, (1991)Phase Error Characteristics of a Second-Order Phase-Lock Loop., and . IEEE Trans. Commun., 23 (6): 687-688 (1975)A novel SVC mechanism for call connection and control in ATM networks., and . Comput. Commun., 20 (12): 1123-1128 (1997)