Author of the publication

Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCs.

, , , and . ISCAS, page 1951-1954. IEEE, (2007)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Digital post-correction of front-end track-and-hold circuits in ADCs., , , and . ISCAS, IEEE, (2006)A 19 µW 20 MHz All-Digital PLL for 2-tone envelope detection radios., , , and . ISCAS, page 321-324. IEEE, (2014)A 30fJ/conversion-step 8b 0-to-10MS/s asynchronous SAR ADC in 90nm CMOS., , , , and . ISSCC, page 388-389. IEEE, (2010)A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction., , and . ISSCC, page 270-271. IEEE, (2013)A Fully-Printed Organic Smart Temperature Sensor for Cold Chain Monitoring Applications., , , , , , and . CICC, page 1-4. IEEE, (2020)A 7.1-fJ/Conversion-Step 88-dB SFDR SAR ADC With Energy-Free "Swap To Reset"., , and . IEEE J. Solid State Circuits, 52 (11): 2979-2990 (2017)A Hybrid Design Automation Tool for SAR ADCs in IoT., , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 26 (12): 2853-2862 (2018)Small-Area SAR ADCs With a Compact Unit-Length DAC Layout., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (10): 4038-4042 (2022)26.2 A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme., , , , , and . ISSCC, page 1-3. IEEE, (2015)Power Optimization for Pipelined ADCs with Open-Loop Residue Amplifiers., , , and . ICECS, page 132-135. IEEE, (2006)