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ASSURE: RTL Locking Against an Untrusted Foundry., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 29 (7): 1306-1318 (2021)ASSURE: RTL Locking Against an Untrusted Foundry., , , , and . CoRR, (2020)A Two-Level Cosimulation Environment., and . Computer, 30 (6): 109-111 (1997)Mine with it or sell it: the superhashing power dilemma., , , and . SIGMETRICS Perform. Evaluation Rev., 46 (3): 127-130 (2018)A light-weight Network-on-Chip architecture for dynamically reconfigurable systems., , , and . ICSAMOS, page 49-56. IEEE, (2008)An adaptive genetic algorithm for dynamically reconfigurable modules allocation., , , and . VLSI-SoC, page 128-133. IEEE, (2007)A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 177-196. Springer, (2006)Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology., , , and . FPT, page 293-296. IEEE, (2006)TaBit: A framework for task graph to bitstream generation., , , , , and . ICSAMOS, page 201-208. IEEE, (2012)Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs., , , , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 179-192. Springer, (2007)