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s PAM-4 SerDes Receiver with 31dB Loss Compensation.

Y. Segal, A. Laufer, A. Khairi, Y. Krupnik, M. Cusmai, I. Levin, A. Gordon, Y. Saban, V. Rahinskj, G. Ori, N. Familia, S. Litski, T. Warshavsky, U. Virobnik, Y. Horwitz, A. Balankutty, S. Kiran, S. Palermo, P. Li, and A. Cohen. ISSCC, page 114-116. IEEE, (2022)

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Mariam Kiran

Kirumakki Narayana Shivaram

Mudnakudu Nagaraju Kiran Kumar

Kiran Varanasi

Shiva Hemmati

Other publications of authors with the same name

A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS.S. Kiran, S. Cai, Y. Luo, S. Hoyos, and S. Palermo. IEEE J. Solid State Circuits, 54 (3): 659-671 (2019)A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels.A. Khairi, Y. Krupnik, A. Laufer, Y. Segal, M. Cusmai, I. Levin, A. Gordon, Y. Sabag, V. Rahinski, I. Lotan and 13 other author(s). IEEE J. Solid State Circuits, 58 (1): 8-18 (2023)A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.Y. Segal, A. Laufer, A. Khairi, Y. Krupnik, M. Cusmai, I. Levin, A. Gordon, Y. Saban, V. Rahinskj, G. Ori and 10 other author(s). ISSCC, page 114-116. IEEE, (2022)A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS.S. Cai, E. Tabasy, A. Shafik, S. Kiran, S. Hoyos, and S. Palermo. VLSIC, page 158-. IEEE, (2015)A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS.S. Cai, E. Tabasy, A. Shafik, S. Kiran, S. Hoyos, and S. Palermo. IEEE J. Solid State Circuits, 52 (8): 2168-2179 (2017)A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET.Y. Zhu, T. Liu, S. Kaile, S. Kiran, I. Yi, R. Liu, J. Diaz, S. Hoyos, and S. Palermo. IEEE J. Solid State Circuits, 58 (8): 2300-2313 (2023)A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS.Y. Zhu, S. Cai, S. Kiran, Y. Fan, P. Chang, S. Hoyos, and S. Palermo. CICC, page 1-4. IEEE, (2020)Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper).J. Diaz, S. Kiran, S. Palermo, and S. Hoyos. MWSCAS, page 1151-1154. IEEE, (2019)A 56GHz Receiver Analog Front End for 224Gb/s PAM-4 SerDes in 10nm CMOS.S. Kiran, A. Balankutty, Y. Liu, R. Dokania, H. Venkataraman, P. Wali, S. Kim, Y. Krupnik, A. Cohen, and F. O'Mahony. VLSI Circuits, page 1-2. IEEE, (2021)A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE.S. Kiran, S. Cai, Y. Luo, S. Hoyos, and S. Palermo. CICC, page 1-4. IEEE, (2019)

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A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.

Please choose a person to relate this publication to

Mariam Kiran

Kirumakki Narayana Shivaram

Mudnakudu Nagaraju Kiran Kumar

Kiran Varanasi

Shiva Hemmati

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Kiran, Shiva"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.

Please choose a person to relate this publication to

Mariam Kiran

Kirumakki Narayana Shivaram

Mudnakudu Nagaraju Kiran Kumar

Kiran Varanasi

Shiva Hemmati

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

A 1.41pJ/b 224Gb/s PAM-4 SerDes Receiver with 31dB Loss Compensation.