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Disambiguation of "Basu, Arindam"

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Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions.

, , , , and . IEEE Trans. Biomed. Circuits Syst., 12 (6): 1410-1421 (2018)

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Arindam Chatterjee

Arindam Khan

Ratna Basu

Ananda Basu

Sumit Basu

 

Other publications of authors with the same name

Robust doublet STDP in a floating-gate synapse., and . IJCNN, page 4296-4301. IEEE, (2014)Hardware and software infrastructure for a family of floating-gate based FPAAs., , , , , , , , and . ISCAS, page 2794-2797. IEEE, (2010)RASP 2.8: A new generation of floating-gate based field programmable analog array., , , , , , , and . CICC, page 213-216. IEEE, (2008)A Fully Integrated Architecture for Fast and Accurate Programming of Floating Gates Over Six Decades of Current., and . IEEE Trans. Very Large Scale Integr. Syst., 19 (6): 953-962 (2011)Domain Wall Motion-Based Dual-Threshold Activation Unit for Low-Power Classification of Non-Linearly Separable Functions., , , , and . IEEE Trans. Biomed. Circuits Syst., 12 (6): 1410-1421 (2018)Dynamics and Bifurcations in a Silicon Neuron., , and . IEEE Trans. Biomed. Circuits Syst., 4 (5): 320-328 (2010)Intelligence Processing Units Accelerate Neuromorphic Learning., , , , , , and . CoRR, (2022)Power-efficient Spike Sorting Scheme Using Analog Spiking Neural Network Classifier., , , , and . ACM J. Emerg. Technol. Comput. Syst., 17 (2): 12:1-12:29 (2021)A 0.11-0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (2): 617-630 (2021)Hardware-Amenable Structural Learning for Spike-Based Pattern Classification Using a Simple Model of Active Dendrites., , and . Neural Comput., 27 (4): 845-897 (2015)