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Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks.

, , , , , и . CoRR, (2021)

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Avradip Mandal

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Soumyajit Mandal

 

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Impact of On-chip Interconnect on In-memory Acceleration of Deep Neural Networks., , , , , и . ACM J. Emerg. Technol. Comput. Syst., 18 (2): 34:1-34:22 (2022)Impact of On-Chip Interconnect on In-Memory Acceleration of Deep Neural Networks., , , , , и . CoRR, (2021)Interconnect-Aware Area and Energy Optimization for In-Memory Acceleration of DNNs., , , , , и . IEEE Des. Test, 37 (6): 79-87 (2020)Achieving Datacenter-scale Performance through Chiplet-based Manycore Architectures., , , , и . DATE, стр. 1-6. IEEE, (2023)Online Adaptive Learning for Runtime Resource Management of Heterogeneous SoCs., , , , , и . DAC, стр. 1-6. IEEE, (2020)A Lightweight Congestion Control Technique for NoCs with Deflection Routing., , , , и . DATE, стр. 1-2. IEEE, (2023)Analytical modeling of NoCs for fast simulation and design exploration (invited)., , , и . SLIP, стр. 8. ACM, (2020)System-Level Benchmarking of Chiplet-based IMC Architectures for Deep Neural Network Acceleration., , , , , и . ASICON, стр. 1-4. IEEE, (2021)Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor., , , , , , , , , и 33 other автор(ы). ISCAS, стр. 443-447. IEEE, (2022)Fast Performance Analysis for NoCs With Weighted Round-Robin Arbitration and Finite Buffers., , , , , и . IEEE Trans. Very Large Scale Integr. Syst., 31 (5): 670-683 (мая 2023)