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Disambiguation of "Fujita, Masahiro"

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Symbolic Model Checking Using SAT Procedures instead of BDDs.

, , , , and . DAC, page 317-320. ACM Press, (1999)

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Toko Fujita

Masahiro Noguchi

Buntaro Fujita

Masahiro Ogawa

Masahiro Yoshida

 

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SAT-based Silicon Debug of Electrical Errors under Restricted Observability Enhancement., , and . J. Electron. Test., 35 (5): 655-678 (2019)Modular Datapath Optimization and Verification Based on Modular-HED., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (9): 1422-1435 (2010)Toward Unification of Synthesis and Verification in Topologically Constrained Logic Design.. Proc. IEEE, 103 (11): 2052-2060 (2015)Solving the net matching problem in high-performance chip design., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 15 (8): 902-911 (1996)Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping., , , , and . Formal Methods Syst. Des., 10 (2/3): 137-148 (1997)Performance Estimation with Automatic False-Path Detection for System-Level Designs., , and . IPSJ Trans. Syst. LSI Des. Methodol., (2010)Synthesis and Generalization of Parallel Algorithm for Matrix-vector Multiplication., , , and . IPSJ Trans. Syst. LSI Des. Methodol., (2020)Kinetic analysis in human brain of 11C(R)-rolipram, a positron emission tomographic radioligand to image phosphodiesterase 4: A retest study and use of an image-derived input function., , , , , , , , and . NeuroImage, 54 (3): 1903-1909 (2011)Temporal Logic Based Hardware Description and Its Verification with Prolog., , and . New Gener. Comput., 1 (2): 195-203 (1983)Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 3192-3199 (2003)