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A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only)., , and . FPGA, page 281. ACM, (2016)Synthesis of low-power selectively-clocked systems from high-level specification., and . ACM Trans. Design Autom. Electr. Syst., 5 (3): 311-321 (2000)Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs., , , , , , and . DATE, page 625-630. EDA Consortium San Jose, CA, USA / ACM DL, (2013)Towards high-performance polarity-controllable FETs with 2D materials., , , , , , , , and . DATE, page 637-641. IEEE, (2018)Scalable Boolean Methods in a Modern Synthesis Flow., , , , , , , , and . DATE, page 1643-1648. IEEE, (2019)Performance analysis of 3-D monolithic integrated circuits., , , , , and . 3DIC, page 1-4. IEEE, (2010)Pattern-based FPGA logic block and clustering algorithm., , and . FPL, page 1-4. IEEE, (2014)System-Level Design for Nano-Electronics., , , , and . ICECS, page 747-751. IEEE, (2007)New Design Paradigms: New Architectures for New technologies.. ICECS, page 1. IEEE, (2007)Parallel vs. serial inter-plane communication using TSVs., , and . LASCAS, page 1-5. IEEE, (2014)