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Disambiguation of "da Costa, Eduardo A. C."

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Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design.

, , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (12): 3126-3137 (2017)

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Afonso da Costa

Alvaro Filipe da Costa

Paulo Eduardo Miranda Costa

Stefania Costache

Stephan Costabel

 

Other publications of authors with the same name

Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms., , and . LASCAS, page 1-4. IEEE, (2013)Design of a radix-2m hybrid array multiplier using carry save adder format., , , and . SBCCI, page 172-177. ACM, (2005)Minimum number of operations under a general number representation for digital filter synthesis., , , and . ECCTD, page 252-255. IEEE, (2007)Exploring Approximate Arithmetic Units for a Power-Efficient Kalman Gain VLSI Design., , , , and . ICECS 2022, page 1-4. IEEE, (2022)The Radix-2m Squared Multiplier., , , , and . ICECS, page 1-4. IEEE, (2020)Optimizing Iterative-based Dividers for an Efficient Natural Logarithm Operator Design., , , , and . LASCAS, page 1-4. IEEE, (2020)An Efficient N-bit 8-2 Adder Compressor with a Constant Internal Carry Propagation Delay., , , , , and . LASCAS, page 1-4. IEEE, (2020)Exploiting adder compressors for power-efficient 2-D approximate DCT realization., , , , and . LASCAS, page 383-386. IEEE, (2016)Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication., , , and . SBCCI, page 1-6. IEEE, (2018)A New Architecture for Signed Radix-2m Pure Array Multipliers., , and . ICCD, page 112-117. IEEE Computer Society, (2002)