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Disambiguation of "Ho, Weng-Geng"

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A comparative study on asynchronous Quasi-Delay-Insensitive templates.

, , , , , and . ISCAS, page 1819-1822. IEEE, (2012)

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Klaus Geng

Hui Geng

Hong Geng

Geng Lai

Reinhard Geng

 

Other publications of authors with the same name

Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation., , , , , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 11 (2): 343-356 (2021)High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)., , , , and . ISCAS, page 1913-1916. IEEE, (2015)Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation., , , , , and . ISCAS, page 1936-1939. IEEE, (2011)Synthesis of asynchronous QDI circuits using synchronous coding specifications., , , , and . ISCAS, page 153-156. IEEE, (2014)A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation., , , and . DSP, page 1-5. IEEE, (2018)Normalized Differential Power Analysis - for Ghost Peaks Mitigation., , , , , , , , and . ISCAS, page 1-5. IEEE, (2021)High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications., , , , and . ISOCC, page 173-174. IEEE, (2020)A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic., , , , , and . ISCAS, page 3022-3025. IEEE, (2013)A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation., , , , and . ISIC, page 320-323. IEEE, (2014)DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer., , , and . ISCAS, page 1-4. IEEE, (2017)